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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74LVC2G34GW-Q100

Dual buffer gate

The 74LVC2G34-Q100 is a dual buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

  • Wide supply voltage range from 1.65 V to 5.5 V

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power dissipation

  • IOFF provides partial Power-down mode operation

  • Direct interface with TTL levels

  • Latch-up performance exceeds 250 mA

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD36 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

參數(shù)類型

型號(hào) VCC (V) Logic switching levels Output drive capability (mA) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74LVC2G34GW-Q100 1.65?-?5.5 CMOS/LVTTL ± 32 175 2 low -40~125 264 38.4 153 TSSOP6

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號(hào) 可訂購(gòu)的器件編號(hào),(訂購(gòu)碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC2G34GW-Q100 74LVC2G34GW-Q100,1
(935299052125)
Active YA SOT363-2
TSSOP6
(SOT363-2)
SOT363-2 SOT363-2_125

環(huán)境信息

型號(hào) 可訂購(gòu)的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74LVC2G34GW-Q100 74LVC2G34GW-Q100,1 74LVC2G34GW-Q100 rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (7)

文件名稱 標(biāo)題 類型 日期
74LVC2G34_Q100 Dual buffer gate Data sheet 2023-08-22
AN11009 Pin FMEA for LVC family Application note 2019-01-09
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02
lvc2g34 74LVC2G34 IBIS model IBIS model 2015-09-06
SOT363-2 plastic thin shrink small outline package; 6 leads; body width 1.25 mm Package information 2022-11-21
SOT363-2_125 TSSOP6 ; Reel pack for SMD, 7"; Q3/T4 product orientation Packing information 2022-11-04
74LVC2G34GW-Q100_Nexperia_Product_Reliability 74LVC2G34GW-Q100 Nexperia Product Reliability Quality document 2024-06-16

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請(qǐng)告知我們并填寫(xiě) 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
lvc2g34 74LVC2G34 IBIS model IBIS model 2015-09-06
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購(gòu)、定價(jià)與供貨

型號(hào) Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購(gòu)買
74LVC2G34GW-Q100 74LVC2G34GW-Q100,1 935299052125 Active SOT363-2_125 3,000 訂單產(chǎn)品

樣品

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如果您沒(méi)有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購(gòu)部件

型號(hào) 可訂購(gòu)的器件編號(hào) 訂購(gòu)代碼(12NC) 封裝 從經(jīng)銷商處購(gòu)買
74LVC2G34GW-Q100 74LVC2G34GW-Q100,1 935299052125 SOT363-2 訂單產(chǎn)品
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