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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)
PSMN1R0-40ULD

PSMN1R0-40ULD

N-channel 40 V, 1.1 mOhm, 280 A logic level Application Specific MOSFET in SOT1023A enhanced package for UL2595

28 January 2025

1. General description

SOT1023A with improved creepage and clearance to meet UL2595 requirements. 280 Amp logic level gate drive N-channel enhancement mode MOSFET in LFPAK56 package. Part of the ASFETs for Battery Isolation and DC Motor control family and using Nexperia’s unique “SchottkyPlus” technology delivers high efficiency and low spiking performance usually associated with MOSFETs with an integrated Schottky or Schottky-like diode but without problematic high leakage current, particularly suited to battery powered appliance applications.

2. Features and benefits

  • Improved creepage and clearance – meets the requirements of UL2595

  • 280 A capability

  • Avalanche rated, 100% tested at IAS = 190 A

  • NextPower-S3 technology delivers 'superfast switching with soft recovery'

  • Low QRR, QG and QGD for high system efficiency and low EMI designs

  • Schottky-Plus body-diode, gives soft switching without the associated high IDSS leakage

  • Optimised for 4.5 V gate drive utilising NextPower-S3 Superjunction technology

  • High reliability LFPAK (Power SO8) package, copper-clip, solder die attach and qualified to 150 °C

  • Exposed leads can be wave soldered, visual solder joint inspection and high quality solder joints

  • Low parasitic inductance and resistance

3. Applications

  • Brushed and brushless motor control

  • Battery powered appliances where enhanced creepage and clearance is required to meet UL2595

  • For non-UL2595 applications please use PSMN1R0-40YLD

4. Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDS

drain-source voltage

25 °C ≤  Tj ≤  150 °C

-

-

40

V

ID

drain current

VGS = 10 V; Tmb = 25 °C; Figure 2

1

-

-

280

A

Ptot

total power dissipation

Tmb = 25 °C; Figure 1

-

-

164

W

Tj

junction temperature

-55

-

150

°C

Static characteristics

RDSon

drain-source on-state resistance

VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Figure 4; Figure 5

-

1.1

1.4

mΩ

VGS = 10 V; ID = 25 A; Tj = 25 °C; Figure 4; Figure 5

-

0.93

1.1

mΩ

Dynamic characteristics

QGD

gate-drain charge

ID = 25 A; VDS = 20 V; VGS = 4.5 V; Figure 6; Figure 7

-

17

-

nC

QG(tot)

total gate charge

-

59

-

nC

5. Pinning information

Pin

Symbol

Description

Simplified outline

Graphic symbol

1

S

source


LFPAK56-UL2595 (SOT1023A)

2

S

source

3

S

source

4

G

gate

mb

D

mounting base; connected to drain

6. Ordering information

Type number

Package

Name

Description

Version

PSMN1R0-40ULD

LFPAK56-UL2595

plastic, single-ended surface-mounted package (LFPAK56); 4 leads; 1.27 mm pitch

SOT1023A

7. Ordering options

Type number

Orderable part number

Packing

Equivalent standard orderable part number

PSMN1R0-40ULD

PSMN1R0-40ULDX

Reel 7" Q1/T1

-

8. Marking

Type number

Marking code

PSMN1R0-40ULD

 
1D04UL

9. Limiting values

Symbol Parameter Conditions Min Typ Max Unit
The drain-source voltage rating is the voltage that a MOSFET can safely sustain between its drain and source in an OFF-state.
VDS
 drain-source voltage
Tj ≥ 25 °C;
Tj ≤ 150 °C
40 V
VDSM
 peak drain-source voltage
tp ≤ 20 ns;
f ≤ 500 kHz;
EDS(AL) ≤ 200 nJ;
0
45 V
The drain-gate voltage rating usually shares the same capability as drain-source voltage.
VDGR
 drain-gate voltage
Tj ≥ 25 °C;
Tj ≤ 150 °C;
RGS = 20 kΩ
40 V
The gate-source voltage rating of the MOSFET refering to the maximum voltage that can be applied across gate-source.
VGS
 gate-source voltage -20 20 V
The total power dissipation capability given against temperature range between mounting base temperature and the max junction temperature.
Ptot
 total power dissipation
-55 °C
150 °C
 164 W
The drain-source current refers to the maximum continuous current through the MOSFET channel in an ON-state.
ID
 drain current
VGS = 10 V;
Tmb = 25 °C;
0
280 A
The pulsed drain current for which max value is given at 10us.
IDM
 peak drain current
0;
tp ≤ 10 µs;
Tmb = 25 °C
1168 A
The storage temperature is the temperature range in which the device can be stored without affecting its reliability.
Tstg
 storage temperature -55 150 °C
The junction temperature of the device refers to the capability of the silicon die of the MOSFET. Junction temperature is given as a range of operational temperatures of the MOSFET.
Tj
 junction temperature -55 150 °C
Tsld(M)
 peak soldering temperature 260 °C
VESD
 electrostatic discharge voltage
0
0 kV
Source-drain diode
The source-drain current is the maximum continous current though the MOSFET body diode (with the MOSFET in OFF-state)
IS
 source current
Tmb = 25 °C
165 A
The pulse current through the body diode of the MOSFET.
ISM
 peak source current
0;
tp ≤ 10 µs;
Tmb = 25 °C
1284 A
Avalanche ruggedness
The single event Avalanche Energy capability of MOSFET at the conditions given.
EDS(AL)S
 non-repetitive drain-source avalanche energy
ID = 85 A;
Vsup ≤ 40 V;
RGS = 50 Ω;
VGS = 10 V;
Tj(init) = 25 °C;
0;
0;
tp = 0.26 ms
570 mJ
IAS
 non-repetitive avalanche current
Vsup ≤ 40 V;
VGS = 10 V;
Tj(init) = 25 °C;
RGS = 50 Ω;
0
190 A


P d e r = P ( t o t ) P t o t ( 25 ° C ) × 100 %

Figure 1. Normalized total power dissipation as a function of mounting base temperature


(1) 280A continuous current has been successfully demonstrated during applications tests. Practically, the current will be limited by PCB, thermal design and operating temperature.

V G S ≥ 10 V

Figure 2. Continuous drain current as a function of mounting base temperature


Tmb = 25 °C; IDM is a single pulse

Figure 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

10. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit
The thermal resistance between the silicon junction and the MOSFET mounting base. Mounting base is sometimes referred to as case in other datasheets.
Rth(j-mb)
 thermal resistance from junction to mounting base 0.66 0.76 K/W
Rth(j-a)
 thermal resistance from junction to ambient 50 K/W


Figure 1. Transient thermal impedance from junction to mounting base as a function of pulse duration


Figure 2. PCB layout for thermal resistance junction to ambient 1” square pad; FR4 Board; 2oz copper


Figure 3. PCB layout for thermal resistance junction to ambient minimum footprint; FR4 Board; 2oz copper

11. Characteristics

Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
The minimum voltage the device is guaranteed to block between the drain and source terminals in the OFF-state.
V(BR)DSS
 drain-source breakdown voltage
ID = 250 µA;
VGS = 0 V;
-55 °C
175 °C
 43.7 V
The gate-source threshold voltage needed for MOSFETs to conduct a certain drain-current at a specific junction temperature. It is temperature dependent and at higher temperatures the threshold value is lower.
VGS(th)
 gate-source threshold voltage
ID = 1 mA;
0;
-55 °C
175 °C
 1.78 V
ΔVGS(th)/ΔT
 gate-source threshold voltage variation with temperature
Tj ≥ 25 °C;
Tj ≤ 150 °C
-5.1 mV/K
The drain-source leakage current when the MOSFET is in OFF-state. It is temperature dependent and gets higher at higher temperatures.
IDSS
 drain leakage current
5 V
40 V
VGS = 0 V;
-55 °C
175 °C
 0.87 µA
The gate-source leakage current normally in nA range. It is temperature dependent and gets higher at higher temperatures.
IGSS
 gate leakage current
VGS = 16 V;
VDS = 0 V;
Tj = 25 °C
100 nA
The resistance of the device in the on-state under the conditions described. Drain-source on resistance varies greatly with both junction temperature and the gate-source voltage (VGS).
RDSon
 drain-source on-state resistance
1.5 V
15 V
1 A
280 A
-55 °C
175 °C
 1.07 mΩ
RG
 gate resistance
f = 1 MHz
1.3 Ω
Dynamic characteristics
The total gate charge of the MOSFET. Covering the full switching transition showing turn-on threshold, linear mode, and fully enhanced stages.
QG(tot)
 total gate charge
1 A
280 A
5 V
35 V
0 V
15 V
 138 nC
The gate-source charge parameter is a part of the switching transition. It is normally used to determine turn-on time.
QGS
 gate-source charge
1 A
280 A
5 V
35 V
VGS = 4.5 V
20.7 nC
QGS(th)
 pre-threshold gate-source charge
ID = 25 A;
VDS = 20 V;
VGS = 4.5 V
12 nC
QGS(th-pl)
 post-threshold gate-source charge
ID = 25 A;
VDS = 20 V;
VGS = 4.5 V
8 nC
The gate-drain charge is a part of the switching transition. It is responsible for how long the switching transition is held at plateu region.
QGD
 gate-drain charge
1 A
280 A
5 V
35 V
VGS = 4.5 V
20.9 nC
VGS(pl)
 gate-source plateau voltage
ID = 25 A;
VDS = 20 V
2.7 V
The capacitance between the gate and the other two terminals (source and drain). The parameter is voltage dependent.
Ciss
 input capacitance
0 V
35 V
VGS = 0 V;
f = 1 MHz;
Tj = 25 °C
8438 pF
The capacitance between the drain and the other two terminals (gate and source). The parameter is voltage dependent.
Coss
 output capacitance
0 V
35 V
VGS = 0 V;
f = 1 MHz;
Tj = 25 °C
1876 pF
The capacitance between the drain and the gate. The parameter is voltage dependent.
Crss
 reverse transfer capacitance
0 V
35 V
VGS = 0 V;
f = 1 MHz;
Tj = 25 °C
315 pF
td(on)
 turn-on delay time
VDS = 20 V;
RL = 0.8 Ω;
VGS = 4.5 V;
RG(ext) = 5 Ω
52 ns
tr
 rise time
VDS = 20 V;
RL = 0.8 Ω;
VGS = 4.5 V;
RG(ext) = 5 Ω
62 ns
td(off)
 turn-off delay time
VDS = 20 V;
RL = 0.8 Ω;
VGS = 4.5 V;
RG(ext) = 5 Ω
65 ns
tf
 fall time
VDS = 20 V;
RL = 0.8 Ω;
VGS = 4.5 V;
RG(ext) = 5 Ω
38 ns
Qoss
 output charge
VGS = 0 V;
VDS = 20 V;
f = 1 MHz;
Tj = 25 °C
51 nC
Source-drain diode
The forward voltage of the MOSFET body diode under the conditions described.
VSD
 source-drain voltage
5 A
1168 A
VGS = 0 V;
-55 °C
175 °C
 0.72 V
The time taken to recover the charge from the anti-parallel diode when it is switched from its conducting state to its reverse biased (diode) state. Reverse recovery time is related to switching performance.
trr
 reverse recovery time
IS = 25 A;
dIS/dt = -100 A/µs;
VGS = 0 V;
VDS = 20 V
48 ns
The total amount of charge recovered from the anti-parallel diode when it is switched from its conducting state to its reverse biased (diode) state. Reverse recovery charge is related to switching performance.
Qr
 recovered charge
5 A
280 A
-1200 A/µs
-100 A/µs
VGS = 0 V;
VDS = 20 V;
0
29.6 nC
ta
 reverse recovery rise time
IS = 25 A;
dIS/dt = -100 A/µs;
VGS = 0 V;
VDS = 20 V
28.6 ns
tb
 reverse recovery fall time
IS = 25 A;
dIS/dt = -100 A/µs;
VGS = 0 V;
VDS = 20 V
23.8 ns


T j = 25 ° C

Figure 1. Output characteristics; drain current as a function of drain-source voltage; typical values


T j = 25 ° C ;       I D = 25 A

Figure 2. Drain-source on-state resistance as a function of gate-source voltage; typical values


V D S = 12 V

Figure 3. Transfer characteristics; drain current as a function of gate-source voltage; typical values


T j = 25 ° C

Figure 4. Drain-source on-state resistance as a function of drain current; typical values


a = R D S o n R D S o n ⁢     ( 25 ° C )

Figure 5. Normalized drain-source on-state resistance factor as a function of junction temperature


Figure 6. Gate charge waveform definitions


T j = 25 ° C ;       I D = 25 A

Figure 7. Gate-source voltage as a function of gate charge; typical values


V G S = 0 V ;       f = 1 M H z

Figure 8. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values


V G S = 0 V

Figure 9. Source current as a function of source-drain voltage; typical values


Figure 10. Reverse recovery timing definition

12. Package outline

Figure 1. Package outline LFPAK56-UL2595 (SOT1023A)

13. Soldering

Figure 1. Reflow soldering footprint for LFPAK56-UL2595 (SOT1023A)

Limited warranty and liability

Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia.